It is the goal of CHDLogic to provide active leadership and support in developing and maintaining affordable Front-End Digital Logic Designs.

 

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Finite State Machine for HS Data Reception

Initially the D-PHY Monitor is in Rx_STOP state receiving LP-11 sequence. Once it detects the transition from LP-11 to LP01 on its differential wire, the D-PHY Monitor transfers to Rx-HS-Rqst state. In this state, the D-PHY Monitor is receiving LP-01 sequence. When D-PHY Monitor detects the transition from LP-01 to LP-00 , it transfers to  Rx-HS-Prpr state. The D-PHY Monitor receives LP-00 for T TERM_EN time interval. At the end of T TERM_EN , the D-PHY Monitor transfers to Rx-HS-Term state. In this state, the D-PHY Monitor receives ZEROs on its differential line. When it detects the SYNC word “1D” , the D-PHY Monitor transfers to Rx-HS-Data state and starts receiving data bursts until detecting LP-11 on the differential line then returns to Rx-STOP state.

The following wave-form shows the simulation results for CHDLogic’s D-PHY Monitor finite state machine.


Simulation Waveform