Finite State Machine for HS Data Transmission

Initially the D-PHY Driver is in Tx_STOP state until upper layer requests high speed data transmission. In this state, the D-PHY Driver transmits  LP-11 sequence of bytes indicating low power mode. On request of HS data transmission, the D-PHY Driver enters Tx-HS-Rqst state and starts transmission of LP-01 sequence for a pre-configured time interval T LPX . At the end of this time interval, the D-PHY Driver transfers to Tx-HS-Prpr state and starts transmitting LP-00 sequence for a pre-configured time interval T HS-PREPARE . At the end of T HS-PREPARE , the D-PHY Driver transfers to Tx-HS-Go state and sends ZEROs for time interval T HS-ZERO. At the end of T HS-ZERO , the D-PHY Driver transfers to Tx-HS-SYNC state for one Byte clock cycle and sends the SYNC word “1D”. Then the D-PHY Driver transfers to Tx-HS-Data state and transmits HS data bursts. At the end of HS data transmission, the D-PHY Driver transmits ZEROs for T HS-TRAIL time and returns to Tx-STOP state.

The following wave-form shows the simulation results for CHDLogic’s D-PHY Driver finite state machine.

Simulation Waveform