Front-End implementation of MIPI C-PHY Driver / Monitor
Front-End Implementation of C-PHY Tx/Rx IPs
Pre-Requisites:
- Logic Design Basics
- Verilog Basics
- Digital Simulation Tool installed
Course Contents:
- MIPI C-PHY Transmitter IP
- MIPI C-PHY Receiver IP
- Data Synchronization
- Error Handling
- Clock Data Recovery (CDR)
- Hardware Coding Guidelines
- Verilog Implementation
- Front-End Verification
Registration Link:
https://forms.gle/gfp3RQNAFuspi9mk8
Course Duration:
Two Months, 3 lectures / week
Course Benefits:
– Interactive live sessions
– Video sessions
– Instructor support
– Certificate of Completion