It is the goal of CHDLogic to provide active leadership and support in developing and maintaining affordable Front-End Digital Logic Designs.

 

Contact

+1-800-456-478-23

411 University St, Seattle

Front-End Implementation of D-PHY Tx/Rx IPs
Pre-Requisites:
  • Logic Design Basics
  • Verilog Basics
  • Digital Simulation Tool installed
Course Contents:
  1. MIPI D-PHY Transmitter IP
  2. MIPI D-PHY Receiver IP
  3. Data Synchronization
  4. Error Handling
  5. Hardware Coding Guidelines
  6. Verilog Implementation
  7. Front-End Verification
Registration Link: 

https://forms.gle/gfp3RQNAFuspi9mk8

Course Duration:

Two Months, 3 lectures / week

Course Benefits:

– Interactive live sessions

– Video sessions

– Instructor support    

– Certificate of Completion

Course Price: $50