Front-End Implementation of MIPS CPU
This course introduces the basic hardware structure of a programmable computer and the basic laws underlying performance evaluation. The student learns how to design the control and data path hardware for a processor, how to make instructions execute simultaneously through pipelining and simple superscalar execution and how to design fast memory and storage systems.
The principles presented in the lectures are reinforced in the laboratory through the design and simulation of the Register Transfer (RT) implementations in verilog.
Pre-Requisites:
- Digital Logic Design
- Computer Organisation
Course Contents:
1- Review on combinational and sequential logic circuits
2- Fundamental concepts and Instructions Set Architecture (ISA)
3- ISA tradeoffs
4- Single cycle micro architecture
5- Single cycle MIPS
6- Multi cycle MIPS
7- Pipelining
8- Memory
9- Parallel computing
Course Duration:
One Month, 3 lectures / week
Course Benefits:
– Interactive live sessions
– Video sessions
– Instructor support
– Certificate of Completion