It is the goal of CHDLogic to provide active leadership and support in developing and maintaining affordable Front-End Digital Logic Designs.

 

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MIPI D-PHY Driver

CHDLogic’s D-PHY provides the communication protocol between a source of the image data (host) and a destination of the image data (device).It can connect megapixels cameras and high resolution displays to an application processor.

CHDLogic implements both D-PHY Driver and D-PHY Monitor compliant with MIPI D-PHY Version 1.2 specifications. They can operate in both Low Power mode and High Speed mode. To enter High Speed mode, CHDLogic’s D-PHY Driver transmits LP-11, LP-01 and LP-00 sequences. The Data lane remains in HS mode until LP-11 is received.

The following simulation shows the transition of the D-PHY driver from Low power mode to High speed mode.


Simulation Waveform