MIPI D-PHY Monitor
MIPI D-PHY Monitor
In High Speed (HS) mode, CHDLogic’s D-PHY Monitor receives data differentially with data rate 1.5 GHz according to MIPI D-PHY specifications version 1.2.
The differential bit is converted to 2-bits through a Rx Dual-Edge Flip Flop. Then these two bits are deserialized to produce one byte delivering one RxByteHS data to upper layer on RxByteClkHS edge. RxByteClkHS is 312 MHz as per MIPI D-PHY specifications version 1.2.
The following simulation wave-form shows the differential wires of CHDLogic’s D-PHY Monitor RxDp and RxDn and the bytes delivered to upper link layer RxDataHS in both Low Power mode and High Speed mode.
Simulation Waveform
