MIPI D-PHY Rx Dual-Edge Flip-Flop

CHDLogic’s D-PHY Monitor uses the Rx Dual-Edge Flip Flop to receive the differental bit corresponding to the received RxDp and RxDn wires. The Rx Dual Edge Flip-Flop delivers two bits data serially to the de-serializer on both edges of high speed RxDDRClkHS_I clock (1.25 GHz for MIPI D-PHY version 1.2 ). The following simulation wave-form shows the inputs and ouptputs of the Rx Dual-Edge FF.