MIPI D-PHY Rx FIFO

The interface between MIPI D-PHY Monitor and the upper Link layer requires a FIFO. CHDLogic’s Rx FIFO sends start of Transmission (SOT) flag to Link layer. The link layer then starts reading from FIFO. MIPI D-PHY Rx FIFO width should be 9 bits. The MSB indicates that data is valid. The SYNC Detector module writes the received bytes in the Rx FIFO plus 1 in the ninth bit to indicate data valid. The write clock is the RxByteHS clock 325 MHz.

The upper Link layer reads data from Rx FIFO with read clock 350 MHz. Since the read clock will be faster than write clock, the FIFO can be empty sometimes. When the Rx FIFO is empty, its output is zero, this means the output data-valid will be 0.

CHDLogic’s D-PHY Rx FIFO uses gray code to encode read/write pointers to eliminate the problem of synchronizing multiple changing bits on a clock edge.

The following simulation wave-form shows the inputs and outputs of CHDLogic’s D-PHY Rx FIFO.

Simulation Waveform