It is the goal of CHDLogic to provide active leadership and support in developing and maintaining affordable Front-End Digital Logic Designs.

 

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Preamble Detector

In High-Speed transmission, the data burst is preceded by the preamble which consists of sequence of all 1’s or all 3’s symbols. This preamble simplifies the start-up of Clock Recovery at the receiver side.

The C-PHY monitor detects the sequence of 1’s or 3’s preamble symbols as shown in the waveform


Simulation Waveform