It is the goal of CHDLogic to provide active leadership and support in developing and maintaining affordable Front-End Digital Logic Designs.

 

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Symbol Encoder

A Symbol Encoder converts one symbol into a Wire State to be sent over the Lane based on the present 3-bit symbol value and the Wire State that was transmitted in the previous UI. The encoder output is shown in the next table according to MIPI CPHY Specifications.

The C-PHY encoder limits the possible voltage states from 8 (2^3) to 6, throwing out the cases where all three lines have the same voltage (111 or 000). This is done to ensure that at least two lines have opposite voltage during every transition. It also forces a voltage state change at every transition. By doing so, it is guaranteed that a clock can be recovered, regardless of what data is being sent.

 

Simulation Waveform